Lake Arrow’s Arrow architecture shots were published, revealing the informed Intel (Tile) project in all its glory. Andreas Schiling on X He shared several photos of Arrow Lake up close, revealing the arrangement of individual tiles Lake arrows and the cores system inside the computing plate.
The first photo reveals the full matrix of the Ultra 200S Intel series processors, with computing plate in the upper left corner, tile and on the bottom, and the SOC and GPU tile on the right. In the lower left and right left corner there are two fillers designed to ensure structural stiffness.
Some of the most significant attractions from the deep analysis of #arrowlake authorMay 5, 2025
Compute Die is a fable on the TSMC N3B bleeding node with a total area of 117.241 mm². The IO and SoC tile are placed on the older N6 TSMC node, with an IO plate with an area of 24.475 mm square and square SOC 86.648 mm. All tiles rest on the base Fabbed Cafele at 22Nm Finfet Node Intela. Arrow Lake is the first Intel architecture, which is completely produced using nodes from a competitor, except for the basic tile.
The next picture shows all subgrays for secondary tiles in the Arrow Lake. Die I/O houses the Thunderbolt 4 controller/Phy display, PCIA Express/Phys and TBT4 Phys. SOC tiles holding display engines, a media engine, more PCIE Phys, buffers and DDR5 memory controllers. The GPU tiles contain four GPU XE cores and XE LPG (ARC Alchemist).
The final picture shows the latest Intel configuration for Arrow Lake, which differs from previous Intel hybrid architecture. For Arrow Lake Intel, he decided on an e-circuit sandwich between the cores P, instead of placing them all in his own cluster, allegedly to reduce thermal hotspots. Four of eight P cores are located on the matrix borders, and the other four live in the middle of the matrix. Four e-cards (in which each has four cores) are sandwich between the external and internal cores of P.
A shot from the Schilling matrix also reveals the cache system for arrows, consisting of 3 MB of L3 cache for fractures (a total of 36 MB) and 3 MB of L2 cache for the e-clergy cluster, from 1.5 MB shared between two cores directly. Interconnect combines two L2 cache clusters (and related cores), which are also responsible for connecting each core cluster with a ring. One of the main Intel updates made of Lake Arrow is to connect e-core clusters with L3 cache made available by the P core, effectively giving e-cache L3.
Arrow Lake is one of the most complicated Intel architectures and the first of the company that introduced a project in the style of chiplet on the desktop computers market. To say, the first Intel attempt on the competition based on stationary chiplet has not been well accepted due to problems related to delay with Interkonnect, which is responsible for combining all tiles. Intel tries to fix the problem using the firmware update. Despite this, his current implementation cannot touch the competitive Ryzen 9000 AMD processors (such as 9800x3D), nor is it enough to even beat their own processors from the 14th generation from the previous generation in games (such as 14900 thousand).
To say all this, the transition to the approach to the chiplet will provide Intel more ways to optimize its architecture on the road, in a more proficient way. Each tile can be developed regardless of others and built with different nodes to improve crops, optimize development and reduce production costs.
