MIT electronics scientists are developing a fresh way to fabricate transistors at the end of prefabricated dies to continually push the limit of chip density

As smaller process nodes become more exorbitant to implement, chip engineers are turning to other ways to escalate the number of transistors that can be packed onto a single die. Somewhat similar to conventional chip layout, one research team has created a way to apply an additional layer of microscopic switches on top of an already completed die, gluing them where power and signals go.

OK, that’s a very scratchy description of the work being done by MIT’s Department of Electrical Engineering and Computer Science, the University of Waterloo, and Samsung Electronics. But when you read the details about it in the press release on this matter, you will see that it is a bit challenging to describe it all in one sentence.

Traditional CMOS chips are made by depositing and then etching repeated layers of different materials onto a wafer of ultrapure silicon. The lowest layer, also called the front end according to MIT, contains the chip’s transistors (or capacitances, in the case of DRAM).

But to work, they must be powered by electricity, and they must be able to read and write data to the groups of transistors that make up logic cells, data registers, and so on. They are made of many layers of metals and insulators, i.e. the back part.

Theoretically you can have more than one layer of transistors, but unfortunately the materials used are very sensitive to the heat used in the manufacturing process. So much so that any normal process would simply destroy the bottom layer once a fresh one was applied. So an MIT-led team turned the problem on its head to find a solution.

In other words, a fresh transistor layer is used on the back. But even this is not enough to protect the sensitive front from the heat. The researchers solved this problem by using a very skinny layer (only 2 nm stout) of amorphous indium oxide in additional transistors.

It requires the exploit of a much lower temperature than conventional materials, which prevents damage to the front. The group also discovered that a layer of ferroelectric hafnium zirconium oxide could then be used to create memory cells.

Final result? A system with a higher transistor density than a system without additional layers. But don’t get too excited just yet. Research still isn’t able to turn all of this into usable circuits, but all chip architectures start life this way.

We’ve already seen researchers discover a way to stack multiple layers of transistors on top of each other, so if future processors can be built using both techniques as well as conventional chip stacking, the transistor density limitation will be exaggerated.

Moore’s Law may have looked a bit shaky in recent years, but work like this suggests that rumors of his death are very much unfounded.

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